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Verilog Tutorial

This document uses short examples to demonstrate the basic Verilog syntax, time delays, and concurrent execution features. We have tried to condense all the interesting and hard parts of Verilog into 15 pages and skip all of the boring stuff like the what is the difference between real and integer data types. Studying this document will enable you to model circuits using simple structural and behavioral Verilog code and provide a solid framework for learning all the details of the language.
If Verilog is a new language for you we recommend getting a copy of "Verilog HDL" by Samir Plantikar. It is a well organized Verilog textbook that is filled with lots of examples.
1.0 Why Use Verilog?
Most Verilog and VHDL books begin with several chapters describing the languages history and advantages. But the arguments boil down to these:

• HDL simulators are better then gate level simulators for 2 reasons: portable model development, and the ability to design complicated test benches that react to outputs from the model under test. Finding a model for a unique component for your particular gate level simulator can be a frustrating task, with an HDL language you can always write your own model. Also most gate level simulators are limited to simple waveform based test benches which complicates the testing of bus and microprocessor interface circuits.
• Verilog is a great low level language. Structural models are easy to design and Behavioral RTL code is pretty good. The syntax is regular and easy to remember. It is the fastest HDL language to learn and use. However *Verilog lacks user defined data types and lacks the interface-object separation of the VHDLs entity-architecture model.
• VHDL is good for designing behavioral models and incorporates some of the modern object oriented techniques. Its syntax is strange and irregular, and the language is difficult to use. Structural models require a lot of code that interferes with the readability of the model.
• C++as an hardware modeling language is excellent choice for high-level behavioral analysis of a system (like evaluating different data flow architectures in a microprocessor). However C++ lacks the basic hardware concepts like knowledge of strengths, connections, and concurrent execution which complicates model generation for lower level simulations.

Choosing Verilog, VHDL, or C++ will be based on availability of tools, models, and in-house expertise. If you are just learning your first HDL language we recommend Verilog because you will be able to quickly become comfortable with the syntax and timing issues of the language..download: Verilog tutorial